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1 of 12 features ? halts and restarts an out-of-control microprocessor ? holds microprocessor in check during power transients ? automatically restarts microprocessor after power failure ? monitors pushbutton for external override ? accurate 5%, 10% or 20% resets for 3.3v systems and 5% or 10% resets for 5.0v systems ? eliminates the need for discrete components ? 3.3v 20% tolerance for use with 3.0v systems ? pin-compatible with the maxim max705/max706 in 8-pin dip, 8-pin soic, and ? -sop ? 8-pin dip, 8-pin soic and 8-pin ? -sop packages ? industrial temper ature range -40 ? c to +85 ? c pin assignment ds1705 and ds1706_r/s/t (*ds1706l and ds1706p) pin description pbrst - pushbutton reset input v cc - power supply gnd - ground in - input nmi - non-maskable interrupt st - strobe input rst - active low reset output *rst - active high reset output (ds1706p and ds1706l only) wds - watchdog status output description the ds1705/ds1706 3.3- or 5.0-volt micromonitor monitors three vital conditions for a microprocessor: power supply, software execution, and external override. a precision te mperature compensated reference and comparator circuit monitor the status of v cc at the device and at an upstream point for maximum protection. when the sense input detects an out-of-tolerance condi tion, a non-maskable interrupt is generated. as the voltage at the device degrades, an internal power fail signal is generated which forces ds1705/ds1706 3.3v and 5.0v micromonito r 19-5212; rev 4/10 www.maxim-ic.com 8-pin ? -sop (118-mil) see mech. drawings section on website rst(*rst) wds pbrst v cc st nmi in gnd 1 2 3 4 8 7 6 5 8-pin dip (300 -mil) pbrst v cc gnd in wds rst st nmi 1 2 3 4 8 7 6 5 8-pin soic (150-mil) 1 2 3 4 8 7 6 5 pbrst v cc gnd in wds rst(*rst) st nmi downloaded from: http:///
ds1705/ds1706 2 of 12 the reset to an active state. when v cc returns to an in-tolerance conditio n, the reset signal is kept in the active state for a minimum of 130 ms to allow the power supply and processor to stabilize. the second function the ds1705/ds1706 performs is pushbutton reset cont rol. the ds1705/ds1706 debounces the pushbutton input and guarantees an act ive reset pulse width of 130 ms minimum. the third function is a watchdog timer. the ds1705/ ds1706 has an internal timer that forces the wds output signal to the active stat e if the strobe input is not driven low prior to time-out. operation power monitor the ds1705/ds1706 detects out-of-tolerance power s upply conditions and wa rns a processor-based system of impending power failure. when v cc falls below the minimum v cc tolerance, a comparator outputs the rst (or rst) signal. rst (or rst) is an excellent control signal for a microprocessor, as processing is stopped at the last possible moment of valid v cc . on power-up, rst (or rst) are kept active for a minimum of 130 ms to allow the power supply and proce ssor to stabilize. pushbutton reset the ds1705/ds1706 provides an input pin for direct conn ection to a pushbutton rese t (see figure 2). the pushbutton reset input requires an active low signal. internally, this input is debounced and timed such that a rst (or rst) signal of at least 130 ms minimu m will be generated. the 130 ms delay commences as the pushbutton reset input is released from the low level. the pushbutton can be initiated by connecting the wds or nmi outputs to the pbrst input as shown in figure 3. non-maskable interrupt the ds1705/ds1706 generates a non-maskable interrupt ( nmi ) for early warning of a power failure. a precision comparator monitors the volta ge level at the in pin relative to an on-chip reference generated by an internal band gap. the in pin is a high impedan ce input allowing for a user-defined sense point. an external resistor voltage di vider network (figure 5) is used to in terface with high voltage signals. this sense point may be derived from a regulated supply or from a higher dc voltage level closer to the main system power input. since the in trip point v tp is 1.25 volts, the proper values for r1 and r2 can be determined by the equation as shown in figure 5. proper operation of th e ds1705/ds1706 requires that the voltage at the in pin be limited to v cc . therefore, the maximum allowabl e voltage at the supply being monitored (v max ) can also be derived as shown in figure 5. a simple approach to solving the equation is to select a value for r2 high enough to keep power c onsumption low, and solve for r1. the flexibility of the in input pin allows for detec tion of power loss at the earlies t point in a power supply system, maximizing the amount of time for system shutdown between nmi and rst (or rst). when the supply being monitored decays to th e voltage sense point, the ds1705/ds1706 pulses the nmi output to the active st ate for a minimum 200 ? s. the nmi power-fail detection circ uitry also has built-in hysteresis of 100 ? v. the supply must be below the volta ge sense point for approximately 5 ? s before a low nmi will be generated. in this way, power supply noise is removed from the monitoring function, preventing false interrupts. during a powe r-up, any detected in pin levels below v tp by the comparator are disabled from genera ting an interrupt until v cc rises to v cctp . as a result, any potential nmi pulse will not be initiated until v cc reaches v cctp . connecting nmi to pbrst would allow non-maskable interrupt to generate an automatic reset when an out-of-tolerance condition occurred in a monitored supply. an example is shown in figure 3. downloaded from: http:///
ds1705/ds1706 3 of 12 watchdog timer the watchdog timer function forces wds signals active when the st input is not clocked within the 1 second time-out period. time-out of the watchdog starts when rst (or rst) becomes inactive. if a high- to-low transition occurs on the st input pin prior to time-out, the watc hdog timer is rese t and begins to time out again. if the watchdog timer is allowed to time out, the wds signal is driven active (low) for a minimum of 130 ms. the st input can be derived from many micr oprocessor outputs. th e typical signals used are the microprocessors address signals, data si gnals, or control signals. when the microprocessor functions normally, these signals w ould, as a matter of rou tine, cause the watchdog to be reset prior to time-out. to guarantee that the watchdog timer does not time out, a high-to-low transition must occur at or less than the minimum watchdog time-out of 1 sec ond. a typical circuit exampl e is shown in figure 6. micromonitor block diagram figure 1 40k ? 180k ? push-button reset figure 2 downloaded from: http:///
ds1705/ds1706 4 of 12 push-button reset controlled by nmi and wds figure 3 timing diagram: pushbutton reset figure 4 non-maskable interr upt circuit example figure 5 v sense = r2 r2 r1 ? x 1.25 v max = tp sense v v x v cc example: v sense = 4.50v at the trip point v cc = 3.3v 1 0 k ? = r2 therefore: 25.1 50.4 x 3.3 = 11.88v maximum 4 . 5 = 10 k 10k r1 ? x 1.25 r1 = 26 k ? downloaded from: http:///
ds1705/ds1706 5 of 12 watchdog timer figure 6 timing diagram: strobe input figure 7 timing diagram: non-maskable interrupt figure 8 downloaded from: http:///
ds1705/ds1706 6 of 12 timing diagram: power-down figure 9 downloaded from: http:///
ds1705/ds1706 7 of 12 timing diagram: power-up figure 10 downloaded from: http:///
ds1705/ds1706 8 of 12 absolute maxi mum ratings voltage range on v cc pin relative to ground -0.5v to +7.0v voltage range on i/o relative to ground* -0.5v to (v cc + 0.5v) operating temperature range -40 ? c to +85 ? c storage temperature range -55 ? c to +125 ? c lead temperature (soldering, 10s) +260 ? c soldering temperature (reflow) lead(pb)-free +260 ? c containing lead(pb) +240 ? c this is a stress rating only and functional ope ration of the device at these or any ot her conditions above those indicated in t he operation sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. * the voltage input on in, st, and pbrst can be exceeded if the i nput current is less than 10 ma . recommended dc operating conditions (t a = -40 ? c to +85 ? c) parameter symbol min typ max units notes supply voltage v cc 1.2 5.5 v 1 st and pbrst input high level v ih 2.0 v cc -0.5 v cc +0.3 v 1, 3 1, 4 st and pbrst input low level v il -0.03 +0.5 v 1 dc electrical characteristics (v cc = 1.2v to 5.5v, t a = -40 ? c to +85 ? c.) parameter symbol min typ max units notes v cc trip point ds1705/ds1706l v cctp 4.50 4.65 4.75 v 1 v cc trip point ds1706 v cctp 4.25 4.40 4.50 v 1 v cc trip point ds1706t v cctp 3.00 3.08 3.15 v 1 v cc trip point ds1706s v cctp 2.85 2.93 3.00 v 1 v cc trip point ds1706p or r v cctp 2.55 2.63 2.70 v 1 input leakage i il -1.0 +1.0 ? a 2 output current @ 2.4v i oh 350 ? a 3 output current @ 0.4v i ol 10 ma 3 output voltage @ -500 ? a v oh v cc -0.3 v cc -0.1 v 3 operating current @ v cc < 5.5v i cc 60 ? a 5 operating current @ v cc < 3.6v i cc 50 ? a 5 in input trip point v tp 1.20 1.25 1.30 v 1 capacitance (t a = +25 ? c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf downloaded from: http:///
ds1705/ds1706 9 of 12 ac electrical characteristics (v cc = 1.2v to 5.5v, t a = -40 ? c to +85 ? c.) parameter symbol min typ max units notes pbrst = v il t pb 150 ns reset active time t rst 130 205 285 ms st pulse width t st 10 ns 6 v cc detect to rst and rst t rpd 5 8 ? s 9 v cc slew rate t f 20 ? s v cc detect to rst and rst t rpu 130 205 285 ms 7 v cc slew rate t r 0 ns pbrst stable low to rst and rst t pdly 250 ns watchdog timeout t td 1.0 1.6 2.2 s 8 vin detect to nmi t ipd 5 8 ? s 9 notes: 1. all voltages are referenced to ground. 2. pbrst is internally pulled up to v cc with an internal impedance of 40 k ?? typical and the st input is internally pulled up to v cc with an internal impedance of 180 k ?? typical. 3. v cc 2.4v. 4. v cc < 2.4v. 5. measured with outputs open and all inputs at v cc or ground. 6. must not exceed t td minimum. 7. t r = 5 ? s. 8. minimum watchdog time-out tested at 2.7v for the 3.3v devices and 4.5v for the 5.0v devices. 9. noise immunity ? pulses < 2 ? s will not cause a reset. downloaded from: http:///
ds1705/ds1706 10 of 12 part marking codes cccccc cccccc ###xx 8-pin dip (300 mil) 8-pin soic (150 mil) 8-pin sop (118 mil) ds170ab yywwrv ###xx ds170ab yywwrv ###xx 170ab ywwrv brand codes code description values ab device type and tolerance 5_, 6_, 6l, 6p, 6r, 6s, 6t (where_ is a blank) yww or yyww date code. i dentifies the year and work week the device was assembled. y, the last digit of the year. yy, the last two digits of the year. ww, the work week (values 01 through 52). rv die revision a letter followed by a number (eg. b1) ###xx lot code three numbers followed by 2 letters cccccc country of assembly a bbreviation of country name. downloaded from: http:///
ds1705/ds1706 11 of 12 ordering information part temp range pin-package version ds1705 epa -40c to +85c 8-pin pdip (300 mils) 5v-5% monitor, /rst, /wds ds1705esa -40c to +85c 8-pin so (150 mils) 5v-5% monitor, /rst, /wds ds1705eua -40c to +85c 8-pin sop (118 mils) 5v-5% monitor, /rst, /wds ds1706 epa -40c to +85c 8-pin pdip (300 mils) 5v-10% monitor, /rst, /wds ds1706esa -40c to +85c 8-pin so (150 mils) 5v-10% monitor, /rst, /wds ds1706eua -40c to +85c 8-pin sop (118 mils) 5v-10% monitor, /rst, /wds ds1706lepa -40c to +85c 8-pin pdip (300 mils) 5v-5% monitor, rst, /wds ds1706lesa -40c to +85c 8-pin so (150 mils) 5v-5% monitor, rst, /wds ds1706leua -40c to +85c 8-pin sop (118 mils) 5v-5% monitor, rst, /wds ds1706pepa -40c to +85c 8-pin pdip (300 mils) 3.3v-20% monitor, rst, /wds ds1706pesa -40c to +85c 8-pin so (150 mils) 3.3v-20% monitor, rst, /wds ds1706peua -40c to +85c 8-pin sop (118 mils) 3.3v-20% monitor, rst, /wds ds1706repa -40c to +85c 8-pin pdip (300 mils) 3.3v-20% monitor, /rst, /wds ds1706resa -40c to +85c 8-pin so (150 mils) 3.3v-20% monitor, /rst, /wds ds1706reua -40c to +85c 8-pin sop (118 mils) 3.3v-20% monitor, /rst, /wds ds1706sepa -40c to +85c 8-pin pdip (300 mils) 3.3v-10% monitor, /rst, /wds ds1706sesa -40c to +85c 8-pin so (150 mils) 3.3v-10% monitor, /rst, /wds ds1706seua -40c to +85c 8-pin sop (118 mils) 3.3v-10% monitor, /rst, /wds ds1706tepa -40c to +85c 8-pin pdip (300 mils) 3.3v-5% monitor, /rst, /wds ds1706tesa -40c to +85c 8-pin so (150 mils) 3.3v-5% monitor, /rst, /wds DS1706TEUA -40c to +85c 8-pin sop (118 mils) 3.3v-5% monitor, /rst, /wds note: devices are also available in a lead(pb)- free/rohs-compliant pac kage. specify lead-free by adding a plus (+) to the part number when ordering. e = -40c to +85c temperature range a = 8-lead device p = plastic dip (300 mils) s = so (150 mils) u = sop (118 mils) package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs stat us only. package drawings may show a di fferent suffix character, but the drawing pertains to the package re gardless of rohs status. package type packag e code document no. 8 pdip p8-2 21-0043 8 so s8-2 21-0041 8 ? sop u8-1 21-0036 downloaded from: http:///
ds1705/ds1706 12 of 12 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim in tegrated products, inc. the dallas logo is a registered trademark of maxim integrate d products, inc. revision history revision date description pages changed 4/10 added the lead temperature and updated the soldering temperature in the absolute maximum ratings ; corrected note 9. 8, 9 downloaded from: http:///

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